verilog-generator: Agent skill for Verilog-2001 RTL generation and FPGA design workflows

by Eriemon · Codex Skill · ★ 237

Last updated: · Indexed by AgentSkillsHub · Auto-synced every 8h

Security audit verdict: SAFE · quality 70/100

None of the 42 rules matched — no credential harvesting, no data exfiltration, no curl-pipe-shell installer. Scanned against 42 published rules built on the SlowMist agent-security taxonomy, refreshed every 8 hours. Full audit →

The quality score combines nine heuristic checks of the repo and its README: completeness, clarity, specificity, examples, structure, agent readiness, step-by-step content, instruction quality and security notes. It rates how well the project explains itself to an agent, not the code.

agent-skillcodex-skilledafpgahardware-generationrtlverilog

Quick Facts

Stars237
Forks12
LanguagePython
CategoryCodex Skill
LicenseApache-2.0
Quality Score70/100
Last Updated2026-08-25
Created2026-05-08
Platformscodex, python
Est. Tokens~15k

About verilog-generator

English  |  中文 Verilog Generator A Codex-ready agent skill for disciplined Verilog-2001 RTL workflows. Verilog Generator turns an AI coding agent into a more reliable RTL engineering assistant.

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How this security grade is produced

Grades come from a rule-based scan built on the SlowMist agent-security taxonomy: 42 published rules, covering credential harvesting, data exfiltration, curl | sh installers and more. It is a first-layer scan, not a manual audit — we say so rather than overstate it.

The scale of the problem is documented independently: Liu et al. (2026), in a study of 31,132 agent skills, report that 26.1% contain security vulnerabilities. Our own full-catalog census is published as a citable open dataset.

Sources & who's responsible:

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